/*!
 *
 * \file    Mxd0250Private.h
 *
 * \brief    SDK private header file. this file must not open to host application layer.
 *
 * Header file of the private declaration about MIRA CMMB Demod SDK
 *
 * \par    Include files
 * - Mxd0250Private.h
 *
 * \par    Copyright (c) 2008 Maxscend Technologies Inc. All rights reserved
 *
 * PROPRIETARY RIGHTS of Maxscend Technologies Inc. are involved in
 * the subject matter of this material.  All manufacturing, reproduction,
 * use, and sales rights pertaining to this subject matter are governed
 * by the license agreement.  The recipient of this software implicitly
 * accepts the terms of the license.
 *
 * \version
 * Revision of last commit: $Rev:: 996                                      $
 * Author of last commit  : $Author:: maxscend\chaohui.jiang                $
 * Date of last commit    : $Date:: 2008-11-17 15:45:38 +0800 (星期?$
 *
 */

#ifndef __MIRA_PRIVATE_H__
#define __MIRA_PRIVATE_H__

#ifdef __cplusplus
extern "C" {
#endif

#include "Mxd0250API.h"


#define REG_HIC1_INT_STATUS 0X00
#define REG_TDP_IR_SFO_UNLOCK_INT_BIT (1<<7)
#define REG_TDP_IR_FTS_FAIL_IN_NORMAL_BIT (1<<6)
#define REG_HIC_IR_SC5_DAT_RDY_STATUS_BIT (1<<5)
#define REG_HIC_IR_SC4_DAT_RDY_STATUS_BIT (1<<4)
#define REG_HIC_IR_SC3_DAT_RDY_STATUS_BIT (1<<3)
#define REG_HIC_IR_SC2_DAT_RDY_STATUS_BIT (1<<2)
#define REG_HIC_IR_SC1_DAT_RDY_STATUS_BIT (1<<1)
#define REG_HIC_IR_SC0_DAT_RDY_STATUS_BIT (1<<0)

#define REG_HIC1_INT_MASK 0X01
#define REG_TDP_IR_SFO_UNLOCK_INT_MASK_BIT (1<<7)
#define REG_TDP_IR_FTS_FAIL_IN_NORMAL_MASK_BIT (1<<6)
#define REG_HIC_IR_SC5_DAT_RDY_MASK_BIT (1<<5)
#define REG_HIC_IR_SC4_DAT_RDY_MASK_BIT (1<<4)
#define REG_HIC_IR_SC3_DAT_RDY_MASK_BIT (1<<3)
#define REG_HIC_IR_SC2_DAT_RDY_MASK_BIT (1<<2)
#define REG_HIC_IR_SC1_DAT_RDY_MASK_BIT (1<<1)
#define REG_HIC_IR_SC0_DAT_RDY_MASK_BIT (1<<0)

#define REG_HIC1_INT_CLEAR 0X02
#define REG_TDP_IR_SFO_UNLOCK_INT_CLEAR_BIT (1<<7)
#define REG_TDP_IR_FTS_FAIL_IN_NORMAL_CLEAR_BIT (1<<6)
#define REG_HIC_IR_SC5_DAT_RDY_CLEAR_BIT (1<<5)
#define REG_HIC_IR_SC4_DAT_RDY_CLEAR_BIT (1<<4)
#define REG_HIC_IR_SC3_DAT_RDY_CLEAR_BIT (1<<3)
#define REG_HIC_IR_SC2_DAT_RDY_CLEAR_BIT (1<<2)
#define REG_HIC_IR_SC1_DAT_RDY_CLEAR_BIT (1<<1)
#define REG_HIC_IR_SC0_DAT_RDY_CLEAR_BIT (1<<0)

#define REG_HIC2_INT_STATUS 0X03
#define REG_HIC_IR_MP2TS_RQ_OVERFLOW_STATUS_BIT (1<<7)
#define REG_HIC_IR_I2C_PHY_ERR_STATUS_BIT (1<<6)
#define REG_HIC_IR_SC5_UNDERFLOW_STATUS_BIT (1<<5)
#define REG_HIC_IR_SC4_UNDERFLOW_STATUS_BIT (1<<4)
#define REG_HIC_IR_SC3_UNDERFLOW_STATUS_BIT (1<<3)
#define REG_HIC_IR_SC2_UNDERFLOW_STATUS_BIT (1<<2)
#define REG_HIC_IR_SC1_UNDERFLOW_STATUS_BIT (1<<1)
#define REG_HIC_IR_SC0_UNDERFLOW_STATUS_BIT (1<<0)

#define REG_HIC2_INT_MASK 0X04
#define REG_HIC_IR_MP2TS_RQ_OVERFLOW_MASK_BIT (1<<7)
#define REG_HIC_IR_I2C_PHY_ERR_MASK_BIT (1<<6)
#define REG_HIC_IR_SC5_UNDERFLOW_MASK_BIT (1<<5)
#define REG_HIC_IR_SC4_UNDERFLOW_MASK_BIT (1<<4)
#define REG_HIC_IR_SC3_UNDERFLOW_MASK_BIT (1<<3)
#define REG_HIC_IR_SC2_UNDERFLOW_MASK_BIT (1<<2)
#define REG_HIC_IR_SC1_UNDERFLOW_MASK_BIT (1<<1)
#define REG_HIC_IR_SC0_UNDERFLOW_MASK_BIT (1<<0)

#define REG_HIC2_INT_CLEAR 0X05
#define REG_HIC_IR_MP2TS_RQ_OVERFLOW_CLEAR_BIT (1<<7)
#define REG_HIC_IR_I2C_PHY_ERR_CLEAR_BIT (1<<6)
#define REG_HIC_IR_SC5_UNDERFLOW_CLEAR_BIT (1<<5)
#define REG_HIC_IR_SC4_UNDERFLOW_CLEAR_BIT (1<<4)
#define REG_HIC_IR_SC3_UNDERFLOW_CLEAR_BIT (1<<3)
#define REG_HIC_IR_SC2_UNDERFLOW_CLEAR_BIT (1<<2)
#define REG_HIC_IR_SC1_UNDERFLOW_CLEAR_BIT (1<<1)
#define REG_HIC_IR_SC0_UNDERFLOW_CLEAR_BIT (1<<0)

#define REG_OTDD_INT_STATUS 0X06
#define REG_TDP_IR_TIMEOUT_INT_STATUS_BIT (1<<6)
#define REG_OTDD_IR_SC5_OVERFLOW_STATUS_BIT (1<<5)
#define REG_OTDD_IR_SC4_OVERFLOW_STATUS_BIT (1<<4)
#define REG_OTDD_IR_SC3_OVERFLOW_STATUS_BIT (1<<3)
#define REG_OTDD_IR_SC2_OVERFLOW_STATUS_BIT (1<<2)
#define REG_OTDD_IR_SC1_OVERFLOW_STATUS_BIT (1<<1)
#define REG_OTDD_IR_SC0_OVERFLOW_STATUS_BIT (1<<0)

#define REG_OTDD_INT_MASK 0X07
#define REG_TDP_IR_TIMEOUT_INT_MASK_BIT (1<<6)
#define REG_OTDD_IR_SC5_OVERFLOW_MASK_BIT (1<<5)
#define REG_OTDD_IR_SC4_OVERFLOW_MASK_BIT (1<<4)
#define REG_OTDD_IR_SC3_OVERFLOW_MASK_BIT (1<<3)
#define REG_OTDD_IR_SC2_OVERFLOW_MASK_BIT (1<<2)
#define REG_OTDD_IR_SC1_OVERFLOW_MASK_BIT (1<<1)
#define REG_OTDD_IR_SC0_OVERFLOW_MASK_BIT (1<<0)

#define REG_OTDD_INT_CLEAR 0X08
#define REG_TDP_IR_TIMEOUT_INT_CLEAR_BIT (1<<6)
#define REG_OTDD_IR_SC5_OVERFLOW_CLEAR_BIT (1<<5)
#define REG_OTDD_IR_SC4_OVERFLOW_CLEAR_BIT (1<<4)
#define REG_OTDD_IR_SC3_OVERFLOW_CLEAR_BIT (1<<3)
#define REG_OTDD_IR_SC2_OVERFLOW_CLEAR_BIT (1<<2)
#define REG_OTDD_IR_SC1_OVERFLOW_CLEAR_BIT (1<<1)
#define REG_OTDD_IR_SC0_OVERFLOW_CLEAR_BIT (1<<0)

#define REG_MISC_INT_STATUS 0X09
#define REG_TDP_IR_FTS_FAIL_IN_INIT_BIT (1<<7)
#define REG_FDP_IR_STC_DONE_STATUS_BIT (1<<6)
#define REG_FDP_IR_STC_OCCUR_INT_STATUS_BIT (1<<5)
#define REG_QBL_IR_REFFW_STATUS_BIT (1<<4)
#define REG_OTDD_IR_CONFIG_NUM_STATUS_BIT (1<<3)
#define REG_OTDD_IR_URGENT_BDCAST_STATUS_BIT (1<<2)
#define REG_OTDD_IR_CRC_ERR_STATUS_BIT (1<<1)
#define REG_OTDD_IR_RS_ERR_INT_STATUS_BIT (1<<0)

#define REG_MISC_INT_MASK 0X0A
#define REG_TDP_IR_FTS_FAIL_IN_INIT_MASK_BIT (1<<7)
#define REG_FDP_IR_STC_DONE_MASK_BIT (1<<6)
#define REG_FDP_IR_STC_OCCUR_INT_MASK_BIT (1<<5)
#define REG_QBL_IR_REFFW_MASK_BIT (1<<4)
#define REG_OTDD_IR_CONFIG_NUM_MASK_BIT (1<<3)
#define REG_OTDD_IR_URGENT_BDCAST_MASK_BIT (1<<2)
#define REG_OTDD_IR_CRC_ERR_MASK_BIT (1<<1)
#define REG_OTDD_IR_RS_ERR_INT_MASK_BIT (1<<0)

#define REG_MISC_INT_CLEAR 0X0B
#define REG_TDP_IR_FTS_FAIL_IN_INIT_CLEAR_BIT (1<<7)
#define REG_FDP_IR_STC_DONE_CLEAR_BIT (1<<6)
#define REG_FDP_IR_STC_OCCUR_INT_CLEAR_BIT (1<<5)
#define REG_QBL_IR_REFFW_CLEAR_BIT (1<<4)
#define REG_OTDD_IR_CONFIG_NUM_CLEAR_BIT (1<<3)
#define REG_OTDD_IR_URGENT_BDCAST_CLEAR_BIT (1<<2)
#define REG_OTDD_IR_CRC_ERR_CLEAR_BIT (1<<1)
#define REG_OTDD_IR_RS_ERR_INT_CLEAR_BIT (1<<0)

#define REG_TIC_CONTROL 0X0C
#define REG_RF_AGC_BYTE_NUM_SHIFT 5
#define REG_RF_AGC_BYTE_NUM_MASK ((1<<2)-1)
#define REG_BB_AGC_BYTE_NUM_SHIFT 3
#define REG_BB_AGC_BYTE_NUM_MASK ((1<<2)-1)
#define REG_I2C_DIRECT_RD_ENABLE_BIT (1<<2)
#define REG_PRESCALE_MSB_BIT (1<<1)
#define REG_I2C_RESTART_EN_BIT (1<<0)

#define REG_SLAVE_ADD 0X0D

#define REG_PRESCALE_COUNTER 0X0E

#define REG_TIC_STATUS 0X0F
#define REG_I2C_DATA_NAK_BIT (1<<3)
#define REG_I2C_SLAVE_ADD_NAK_BIT (1<<2)
#define REG_AGC_LUT_RD_READY_BIT (1<<1)
#define REG_SLAVE_OP_FINISH_BIT (1<<0)

#define REG_TIC_HOST_ACCESS_BYTE_NUM 0X10
#define REG_SLAVE_HIGH_SUBADD_VLD_BIT (1<<6)
#define REG_HW_BYTE_NUM_SHIFT 3
#define REG_HW_BYTE_NUM_MASK ((1<<3)-1)
#define REG_HR_BYTE_NUM_SHIFT 0
#define REG_HR_BYTE_NUM_MASK ((1<<3)-1)

#define REG_SLAVE_HIGH_ADD 0X11

#define REG_SLAVE_WRDATA_D 0X12

#define REG_SLAVE_WRDATA_C 0X13

#define REG_SLAVE_WRDATA_B 0X14

#define REG_SLAVE_WRDATA_A 0X15

#define REG_SLAVE_WRADD 0X16

#define REG_SLAVE_RDADD 0X17

#define REG_SLAVE_RDDATA_D 0X18

#define REG_SLAVE_RDDATA_C 0X19

#define REG_SLAVE_RDDATA_B 0X1A

#define REG_SLAVE_RDDATA_A 0X1B

#define REG_TUNER_RF_AGC_ADD 0X1C

#define REG_TUNER_BB_AGC_ADD 0X1D

#define REG_AGC_MASK_H 0X1E

#define REG_AGC_MASK_L 0X1F

#define REG_AGC_LUT_WRDATA_H 0X20

#define REG_AGC_LUT_WRDATA_L 0X21

#define REG_AGC_LUT_WRADD 0X22

#define REG_AGC_LUT_RDADD 0X23

#define REG_AGC_LUT_RDDATA_H 0X24

#define REG_AGC_LUT_RDDATA_L 0X25

#define REG_TIC_LPC_CONTROL 0X26
#define REG_LPC_BYTE_NUM_SHIFT 2
#define REG_LPC_BYTE_NUM_MASK ((1<<2)-1)
#define REG_LPC_PIN_ENABLE_BIT (1<<1)
#define REG_LPC_PIN_INFO_BIT (1<<0)

#define REG_TUNER_LPC_ADD 0X27

#define REG_TUNER_LPC_ACTIVE_DATA_H 0X28

#define REG_TUNER_LPC_ACTIVE_DATA_L 0X29

#define REG_TUNER_LPC_LP_DATA_H 0X2A

#define REG_TUNER_LPC_LP_DATA_L 0X2B

#define REG_CHE_CFG 0X2C

#define REG_CHE_STATUS 0X2D

#define REG_TXID_DONE 0X2E

#define REG_TXID_AREA_ID 0X2F

#define REG_TXID_TRANSMIT_ID 0X30

#define REG_DIVERSITY_STATUS 0X31

#define REG_DUAL_ANTENNA_DELAY 0X32

#define REG_IFFT_IN_SHIFT 0X33

#define REG_DATAPATH_FIX_CFG 0X34

#define REG_BYDI_SYNC_DONE 0X35

#define REG_STORE_HN_CONTROL 0X36
#define REG_HN_RESET_BIT (1<<1)
#define REG_STORE_HN_BIT (1<<0)

#define REG_HN_READY 0X37

#define REG_IFO2_WINDOW_WIDTH 0X38

#define REG_COEFF_IDX 0X39

#define REG_CHIP_VERSION 0X3A

#define REG_FREEZE_CTRL 0X3B
#define REG_SFO_FREEZE_BIT (1<<3)
#define REG_QBL_BLER_FREEZE_BIT (1<<2)
#define REG_NCO_OFT_FREEZE_BIT (1<<1)
#define REG_FTS_FREEZE_BIT (1<<0)

#define REG_DEBUG_SEL 0X3C
#define REG_TOP_DEBUG_SEL_SHIFT 4
#define REG_TOP_DEBUG_SEL_MASK ((1<<4)-1)
#define REG_SUB_DEBUG_SEL_SHIFT 0
#define REG_SUB_DEBUG_SEL_MASK ((1<<4)-1)

#define REG_SOFT_RST 0X3D
#define REG_PHY_MST_RST_N_BIT (1<<5)
#define REG_MP2TS_RST_N_BIT (1<<5)
#define REG_TIC_RST_N_BIT (1<<4)
#define REG_OTDD_RST_N_BIT (1<<3)
#define REG_QBL_RST_N_BIT (1<<2)
#define REG_FDP_RST_N_BIT (1<<1)
#define REG_TDP_RST_N_BIT (1<<0)

#define REG_SOFT_TMP_REG 0X3E

#define REG_DAGC_VAL 0X3F
#define REG_DAGC_S_VAL_SHIFT 4
#define REG_DAGC_S_VAL_MASK ((1<<4)-1)
#define REG_DAGC_U_VAL_SHIFT 0
#define REG_DAGC_U_VAL_MASK ((1<<4)-1)

#define REG_SC_INFO_A 0X40
#define REG_SC0_QAM_TYPE_SHIFT 0
#define REG_SC0_QAM_TYPE_MASK ((1<<2)-1)
#define REG_SC0_CODE_RATE_BIT (1<<2)
#define REG_SC1_QAM_TYPE_SHIFT 3
#define REG_SC1_QAM_TYPE_MASK ((1<<2)-1)
#define REG_SC1_CODE_RATE_BIT (1<<5)

#define REG_SC_INFO_B 0X41
#define REG_SC2_QAM_TYPE_SHIFT 0
#define REG_SC2_QAM_TYPE_MASK ((1<<2)-1)
#define REG_SC2_CODE_RATE_BIT (1<<2)
#define REG_SC3_QAM_TYPE_SHIFT 3
#define REG_SC3_QAM_TYPE_MASK ((1<<2)-1)
#define REG_SC3_CODE_RATE_BIT (1<<5)

#define REG_SC_INFO_C 0X42
#define REG_SC4_QAM_TYPE_SHIFT 0
#define REG_SC4_QAM_TYPE_MASK ((1<<2)-1)
#define REG_SC4_CODE_RATE_BIT (1<<2)
#define REG_SC5_QAM_TYPE_SHIFT 3
#define REG_SC5_QAM_TYPE_MASK ((1<<2)-1)
#define REG_SC5_CODE_RATE_BIT (1<<5)

#define REG_QAM_DEMAP_BITCUT 0X43

#define REG_AUTOSCALE_REFBITWIDTH_FW_H 0X44

#define REG_AUTOSCALE_REFBITWIDTH_FW_L 0X45

#define REG_AUTOSCALE_CONFIG 0X46
#define REG_AUTOSCALE_EN_SHIFT 6
#define REG_AUTOSCALE_EN_MASK ((1<<2)-1)
#define REG_AUTOSCALE_ALPHA_FW_SHIFT 3
#define REG_AUTOSCALE_ALPHA_FW_MASK ((1<<3)-1)
#define REG_AUTOSCALE_ALPHA_BW_SHIFT 0
#define REG_AUTOSCALE_ALPHA_BW_MASK ((1<<3)-1)

#define REG_AUTOSCALE_BITWIDTH_DEFAULT 0X47

#define REG_AUTOSCALE_SCALEMAX 0X48

#define REG_AUTOSCALE_SCALEMIN 0X49

#define REG_AUTOSCALE_BW_CONFIG 0X4A
#define REG_AUTOSCALE_SCALESTEP_SHIFT 1
#define REG_AUTOSCALE_SCALESTEP_MASK ((1<<3)-1)
#define REG_AUTOSCALE_LPF_METHOD_BIT (1<<0)

#define REG_AUTOSCALE_STEPSIGN 0X4B

#define REG_AUTOSCALE_SCALEINTRK 0X4C
#define REG_AUTOSCALE_SCALEINTRK_A_BIT (1<<3)
#define REG_AUTOSCALE_SCALEINTRK_B_BIT (1<<2)
#define REG_AUTOSCALE_SCALEINTRK_C_BIT (1<<1)
#define REG_AUTOSCALE_SCALEINTRK_D_BIT (1<<0)

#define REG_AUTOSCALE_BITWIDTH 0X4D

#define REG_AUTOSCALE_AVER_ITERNUM_A_H 0X4E

#define REG_AUTOSCALE_AVER_ITERNUM_A_L 0X4F

#define REG_AUTOSCALE_AVER_ITERNUM_B_H 0X50

#define REG_AUTOSCALE_AVER_ITERNUM_B_L 0X51

#define REG_AUTOSCALE_AVER_ITERNUM_C_H 0X52

#define REG_AUTOSCALE_AVER_ITERNUM_C_L 0X53

#define REG_AUTOSCALE_AVER_ITERNUM_D_H 0X54

#define REG_AUTOSCALE_AVER_ITERNUM_D_L 0X55

#define REG_AUTOSCALE_FWBITWIDTH 0X56

#define REG_AUTOSCALE_PRECISION 0X57

#define REG_LDPC_CONFIG 0X58
#define REG_LDPC_ITERNUM_SC_NUM_SHIFT 3
#define REG_LDPC_ITERNUM_SC_NUM_MASK ((1<<3)-1)
#define REG_QAM_DEMAP_REVERSE_BIT (1<<2)
#define REG_LDPC_FORCE_ITER_MAX_BIT (1<<1)
#define REG_LDPC_ITER_MODE_BIT (1<<0)

#define REG_LDPC_STA_SIZE 0X59

#define REG_LDPC_ITER_NUM_2QAM 0X5A

#define REG_LDPC_ITER_NUM_4QAM 0X5B

#define REG_LDPC_ITER_NUM_16QAM 0X5C

#define REG_BLER_H 0X5D

#define REG_BLER_L 0X5E

#define REG_ITER_NUM 0X5F

#define REG_SC0_CONFIG_A 0X60
#define REG_SC0_SLCH_CRC_EN_BIT (1<<7)
#define REG_SC0_DEINT_MODE_SHIFT 5
#define REG_SC0_DEINT_MODE_MASK ((1<<2)-1)
#define REG_SC0_BLK_NUM_SHIFT 0
#define REG_SC0_BLK_NUM_MASK ((1<<5)-1)

#define REG_SC0_CONFIG_B 0X61
#define REG_SC0_RS_TYPE_SHIFT 5
#define REG_SC0_RS_TYPE_MASK ((1<<3)-1)
#define REG_SC0_START_BLK_SHIFT 0
#define REG_SC0_START_BLK_MASK ((1<<5)-1)

#define REG_SC1_CONFIG_A 0X62
#define REG_SC1_SLCH_CRC_EN_BIT (1<<7)
#define REG_SC1_DEINT_MODE_SHIFT 5
#define REG_SC1_DEINT_MODE_MASK ((1<<2)-1)
#define REG_SC1_BLK_NUM_SHIFT 0
#define REG_SC1_BLK_NUM_MASK ((1<<5)-1)

#define REG_SC1_CONFIG_B 0X63
#define REG_SC1_RS_TYPE_SHIFT 5
#define REG_SC1_RS_TYPE_MASK ((1<<3)-1)
#define REG_SC1_START_BLK_SHIFT 0
#define REG_SC1_START_BLK_MASK ((1<<5)-1)

#define REG_SC2_CONFIG_A 0X64
#define REG_SC2_SLCH_CRC_EN_BIT (1<<7)
#define REG_SC2_DEINT_MODE_SHIFT 5
#define REG_SC2_DEINT_MODE_MASK ((1<<2)-1)
#define REG_SC2_BLK_NUM_SHIFT 0
#define REG_SC2_BLK_NUM_MASK ((1<<5)-1)

#define REG_SC2_CONFIG_B 0X65
#define REG_SC2_RS_TYPE_SHIFT 5
#define REG_SC2_RS_TYPE_MASK ((1<<3)-1)
#define REG_SC2_START_BLK_SHIFT 0
#define REG_SC2_START_BLK_MASK ((1<<5)-1)

#define REG_SC3_CONFIG_A 0X66
#define REG_SC3_SLCH_CRC_EN_BIT (1<<7)
#define REG_SC3_DEINT_MODE_SHIFT 5
#define REG_SC3_DEINT_MODE_MASK ((1<<2)-1)
#define REG_SC3_BLK_NUM_SHIFT 0
#define REG_SC3_BLK_NUM_MASK ((1<<5)-1)

#define REG_SC3_CONFIG_B 0X67
#define REG_SC3_RS_TYPE_SHIFT 5
#define REG_SC3_RS_TYPE_MASK ((1<<3)-1)
#define REG_SC3_START_BLK_SHIFT 0
#define REG_SC3_START_BLK_MASK ((1<<5)-1)

#define REG_SC4_CONFIG_A 0X68
#define REG_SC4_SLCH_CRC_EN_BIT (1<<7)
#define REG_SC4_DEINT_MODE_SHIFT 5
#define REG_SC4_DEINT_MODE_MASK ((1<<2)-1)
#define REG_SC4_BLK_NUM_SHIFT 0
#define REG_SC4_BLK_NUM_MASK ((1<<5)-1)

#define REG_SC4_CONFIG_B 0X69
#define REG_SC4_RS_TYPE_SHIFT 5
#define REG_SC4_RS_TYPE_MASK ((1<<3)-1)
#define REG_SC4_START_BLK_SHIFT 0
#define REG_SC4_START_BLK_MASK ((1<<5)-1)

#define REG_SC5_CONFIG_A 0X6A
#define REG_SC5_SLCH_CRC_EN_BIT (1<<7)
#define REG_SC5_DEINT_MODE_SHIFT 5
#define REG_SC5_DEINT_MODE_MASK ((1<<2)-1)
#define REG_SC5_BLK_NUM_SHIFT 0
#define REG_SC5_BLK_NUM_MASK ((1<<5)-1)

#define REG_SC5_CONFIG_B 0X6B
#define REG_SC5_RS_TYPE_SHIFT 5
#define REG_SC5_RS_TYPE_MASK ((1<<3)-1)
#define REG_SC5_START_BLK_SHIFT 0
#define REG_SC5_START_BLK_MASK ((1<<5)-1)

#define REG_OTDD_MISC_CTRL 0X6C
#define REG_DBG_ERR_BYTE_CNT_EN_BIT (1<<2)
#define REG_SC5_CLCH_BIT (1<<1)
#define REG_ADVC_MODE_EN_BIT (1<<0)

#define REG_CONCATENATE_RS_ERR_NUM_H 0X6D

#define REG_CONCATENATE_RS_ERR_NUM_L 0X6E

#define REG_RS_NUM_H 0X6F

#define REG_RS_NUM_L 0X70

#define REG_RSD_8ERRNUM_H 0X71

#define REG_RSD_8ERRNUM_L 0X72

#define REG_RS_CHECK_PASS_NUM_H 0X73

#define REG_RS_CHECK_PASS_NUM_L 0X74

#define REG_DBG_ERR_BYTE_NUM_H 0X75

#define REG_DBG_ERR_BYTE_NUM_M 0X76

#define REG_DBG_ERR_BYTE_NUM_L 0X77

#define REG_BER_BYDI_BLK_NUM 0X78

#define REG_SC_URGENT_BDCAST 0X79

#define REG_SC_CONFIG_NUM_A 0X7A

#define REG_SC_CONFIG_NUM_B 0X7B

#define REG_SC_CONFIG_NUM_C 0X7C

#define REG_SC0_SC1_THR 0X86

#define REG_SC2_SC3_THR 0X87

#define REG_SC4_SC5_THR 0X88

#define REG_CH0_DATA_AVAIL_CNT_H 0X89

#define REG_CH0_DATA_AVAIL_CNT_L 0X8A

#define REG_CH1_DATA_AVAIL_CNT_H 0X8B

#define REG_CH1_DATA_AVAIL_CNT_L 0X8C

#define REG_CH2_DATA_AVAIL_CNT_H 0X8D

#define REG_CH2_DATA_AVAIL_CNT_L 0X8E

#define REG_CH3_DATA_AVAIL_CNT_H 0X8F

#define REG_CH3_DATA_AVAIL_CNT_L 0X90

#define REG_CH4_DATA_AVAIL_CNT_H 0X91

#define REG_CH4_DATA_AVAIL_CNT_L 0X92

#define REG_CH5_DATA_AVAIL_CNT_H 0X93

#define REG_CH5_DATA_AVAIL_CNT_L 0X94

#define REG_SDIO_I2C_CTRL 0X95
#define REG_I2C_PT_EN_BIT (1<<7)
#define REG_TIC_PE_BIT (1<<6)
#define REG_SDIO_INT_PE_BIT (1<<5)
#define REG_SDIO_PE_BIT (1<<4)
#define REG_FUNC1_SDIO_INT_BYPASS_BIT (1<<3)
#define REG_FUNC1_SDIO_INT_HLACTV_BIT (1<<2)
#define REG_FUNC1_SDIO_SPI_CPHA_BIT (1<<1)
#define REG_FUNC1_SDIO_SPI_CPOL_BIT (1<<0)

#define REG_MP2TS_CTRL 0X96
#define REG_MP2TS_USE_BIT (1<<5)
#define REG_MP2TS_BANDWIDTH_BIT (1<<4)
#define REG_MP2TS_CLK_ON_BIT (1<<3)
#define REG_MP2TS_CLK_POL_BIT (1<<2)
#define REG_MP2TS_PARA_MODE_BIT (1<<1)
#define REG_MP2TS_MSB_BIT (1<<0)

#define REG_MP2TS_GAP 0X97

#define REG_MISC_CTRL 0X9A
#define REG_TDP_CLK_GATE_EN_BIT (1<<7)
#define REG_FDP_CLK_GATE_EN_BIT (1<<6)
#define REG_QBL_CLK_GATE_EN_BIT (1<<5)
#define REG_OTDD_CLK_GATE_EN_BIT (1<<5)
#define REG_RBUS_CLK_GATE_EN_BIT (1<<3)
#define REG_HIC_CLK_GATE_EN_BIT (1<<2)
#define REG_TIC_CLK_GATE_EN_BIT (1<<1)
#define REG_DUAL_ANT_EN_BIT (1<<0)

#define REG_ADC_MODE_CTRL 0X9B
#define REG_PLL_OUT_EN_BIT (1<<7)
#define REG_MODE_CTRL_ALWAYSON_BIT (1<<6)
#define REG_MODE_CTRL_ENSTANDBY_BIT (1<<5)
#define REG_MODE_CTRL_ENVCM_BIT (1<<4)
#define REG_MODE_CTRL_ENVRF_BIT (1<<3)
#define REG_MODE_CTRL_ENSH_BIT (1<<2)
#define REG_MODE_CTRL_ENIBIAS_BIT (1<<1)
#define REG_MODE_CTRL_GAIN_BIT (1<<0)

#define REG_ADC_TEST_PINS 0X9C
#define REG_ADC_NEGEDGE_BIT (1<<5)
#define REG_ADC_IQ_REVERSE_BIT (1<<4)
#define REG_TEST_PINS_ENDECI_BIT (1<<3)
#define REG_TEST_PINS_ENCTR2_BIT (1<<2)
#define REG_TEST_PINS_ENCTR1_BIT (1<<1)
#define REG_TEST_PINS_ENCTR0_BIT (1<<0)

#define REG_IFO_M 0X9D

#define REG_SEED_INDEX 0X9E

#define REG_SEED_H 0X9F

#define REG_SEED_L 0XA0

#define REG_SC_01_SEED_NUM 0XA1
#define REG_SC_1_SEED_NUM_SHIFT 3
#define REG_SC_1_SEED_NUM_MASK ((1<<3)-1)
#define REG_SC_0_SEED_NUM_SHIFT 0
#define REG_SC_0_SEED_NUM_MASK ((1<<3)-1)

#define REG_SC_23_SEED_NUM 0XA2
#define REG_SC_3_SEED_NUM_SHIFT 3
#define REG_SC_3_SEED_NUM_MASK ((1<<3)-1)
#define REG_SC_2_SEED_NUM_SHIFT 0
#define REG_SC_2_SEED_NUM_MASK ((1<<3)-1)

#define REG_SC_45_SEED_NUM 0XA3
#define REG_SC_5_SEED_NUM_SHIFT 3
#define REG_SC_5_SEED_NUM_MASK ((1<<3)-1)
#define REG_SC_4_SEED_NUM_SHIFT 0
#define REG_SC_4_SEED_NUM_MASK ((1<<3)-1)

#define REG_STC_ST_THR 0XA4

#define REG_STC_ST_IDX_H 0XA5

#define REG_STC_ST_IDX_L 0XA6

#define REG_STC_ST_STR 0XA7

#define REG_STC_ST_WID 0XA8

#define REG_STC_CFIG_IDX_H 0XA9
#define REG_STC1_CFIG_IDX_H_SHIFT 4
#define REG_STC1_CFIG_IDX_H_MASK ((1<<4)-1)
#define REG_STC0_CFIG_IDX_H_SHIFT 0
#define REG_STC0_CFIG_IDX_H_MASK ((1<<4)-1)

#define REG_STC0_CFIG_IDX_L 0XAA

#define REG_STC1_CFIG_IDX_L 0XAB

#define REG_STC_MISC_CTRL 0XAC
#define REG_STC0_NOTCH_EN_BIT (1<<7)
#define REG_STC0_SLOT_WIDTH_SHIFT 4
#define REG_STC0_SLOT_WIDTH_MASK ((1<<3)-1)
#define REG_STC1_NOTCH_EN_BIT (1<<3)
#define REG_STC1_SLOT_WIDTH_SHIFT 0
#define REG_STC1_SLOT_WIDTH_MASK ((1<<3)-1)

#define REG_DAGC_ACC_NUM 0XAD

#define REG_DAGC_BR_VAL 0XAE

#define REG_DAGC_FTS_CTRL 0XAF
#define REG_FTS_FAIL_TIME_THD_SHIFT 5
#define REG_FTS_FAIL_TIME_THD_MASK ((1<<3)-1)
#define REG_DAGC_BYPASS_BIT (1<<4)
#define REG_DAGC_ALPHA_SHIFT 2
#define REG_DAGC_ALPHA_MASK ((1<<2)-1)
#define REG_DAGC_KEXI_SHIFT 0
#define REG_DAGC_KEXI_MASK ((1<<2)-1)

#define REG_SFO_FRZ_VAL_H 0XB0

#define REG_SFO_FRZ_VAL_M 0XB1

#define REG_SFO_FRZ_VAL_L 0XB2

#define REG_AGC_RF_INIT_VAL 0XB3

#define REG_RF_MISC 0XB4
#define REG_AGC_RF_ENABLE_BIT (1<<4)
#define REG_AGC_RF_MAX_VAL_SHIFT 0
#define REG_AGC_RF_MAX_VAL_MASK ((1<<4)-1)

#define REG_AGC_BB_BACK_OFF_STEP 0XB5

#define REG_AGC_BB_DOWN_BOUNDARY 0XB6

#define REG_AGC_BB_UP_BOUNDARY 0XB7

#define REG_NCO_FRZ_IFO2_VAL 0XB8

#define REG_FTS_CHE_SWITCH_THRD1_VAL 0XB9

#define REG_FTS_CHE_SWITCH_THRD2_VAL 0XBA

#define REG_FTS_CHE_SWITCH_THRD3_VAL 0XBB

#define REG_FTS_CHE_SWITCH_THRD4_VAL 0XBC

#define REG_FTS_CHE_SWITCH_THRD5_VAL 0XBD

#define REG_FTS_CHE_SWITCH_OFT 0XBE
#define REG_FTS_CHE_SWITCH_THRD4_OFT_SHIFT 6
#define REG_FTS_CHE_SWITCH_THRD4_OFT_MASK ((1<<2)-1)
#define REG_FTS_CHE_SWITCH_THRD3_OFT_SHIFT 4
#define REG_FTS_CHE_SWITCH_THRD3_OFT_MASK ((1<<2)-1)
#define REG_FTS_CHE_SWITCH_THRD2_OFT_SHIFT 2
#define REG_FTS_CHE_SWITCH_THRD2_OFT_MASK ((1<<2)-1)
#define REG_FTS_CHE_SWITCH_THRD1_OFT_SHIFT 0
#define REG_FTS_CHE_SWITCH_THRD1_OFT_MASK ((1<<2)-1)

#define REG_FTS_CHE_SWITCH_TIME_CFG 0XBF
#define REG_FTS_CHE_SWITCH_THRD5_OFT_SHIFT 4
#define REG_FTS_CHE_SWITCH_THRD5_OFT_MASK ((1<<2)-1)
#define REG_FTS_CHE_SWITCH_HIGH_THD_SHIFT 2
#define REG_FTS_CHE_SWITCH_HIGH_THD_MASK ((1<<2)-1)
#define REG_FTS_CHE_SWITCH_LOW_THD_SHIFT 0
#define REG_FTS_CHE_SWITCH_LOW_THD_MASK ((1<<2)-1)

#define REG_RSSI_VAL_L 0XC0

#define REG_RSSI_VAL_H 0XC1

#define REG_AGC_CFG 0XC2
#define REG_AGC_BYPASS_BIT (1<<7)
#define REG_AGC_WINDOW_SIZE_SHIFT 5
#define REG_AGC_WINDOW_SIZE_MASK ((1<<2)-1)
#define REG_AGC_AFLT_TYPE_SHIFT 2
#define REG_AGC_AFLT_TYPE_MASK ((1<<3)-1)
#define REG_AGC_PARA_K_SHIFT 0
#define REG_AGC_PARA_K_MASK ((1<<2)-1)

#define REG_AGC_PARA_N 0XC3

#define REG_AGC_IQREF_L 0XC4

#define REG_AGC_IQREF_H 0XC5

#define REG_NCO_IFO_BYPASS_VAL 0XC6

#define REG_AGC_INIT_DB 0XC7

#define REG_AGC_MIN_DB 0XC8

#define REG_AGC_MAX_DB 0XC9

#define REG_PDM_ACC_VALUE 0XCA

#define REG_CLP_STATUS 0XCB
#define REG_SFO_SLOW_TRACK_BIT (1<<6)
#define REG_AGC_LOCK_BIT (1<<5)
#define REG_CTS_PASS_BIT (1<<4)
#define REG_CTS_FAIL_BIT (1<<3)
#define REG_FTS_PASS_BIT (1<<2)
#define REG_FTS_FAIL_BIT (1<<1)
#define REG_TSD_DONE_BIT (1<<0)

#define REG_PDM_THRESHOLD_L 0XCC

#define REG_PDM_THRESHOLD_H 0XCD

#define REG_MISC_CFG 0XCE
#define REG_AUTO_CLCH_EN_BIT (1<<7)
#define REG_AGC_RSSI_EN_BIT (1<<6)
#define REG_PDM_POL_SEL_BIT (1<<5)
#define REG_PDM_OEN_BIT (1<<4)
#define REG_AGC_PGA_EN_BIT (1<<3)
#define REG_DC_STEP_SHIFT 0
#define REG_DC_STEP_MASK ((1<<3)-1)

#define REG_NCO_INIT_FREQ_OFT_L 0XCF

#define REG_NCO_INIT_FREQ_OFT_M 0XD0

#define REG_NCO_INIT_FREQ_OFT_H 0XD1

#define REG_NCO_FRZ_FFO_RFO_L 0XD2

#define REG_NCO_FRZ_FFO_RFO_H 0XD3

#define REG_NCO_FRZ_IFO_L 0XD4

#define REG_NCO_FRZ_IFO_H 0XD5

#define REG_CTS_WINDOW_SIZE 0XD6

#define REG_INIT 0XD7
#define REG_TIM_CLR_BIT (1<<2)
#define REG_STC_INIT_BIT (1<<1)
#define REG_CTS_INIT_BIT (1<<0)

#define REG_CTS_PRE_NUM 0XD8

#define REG_HOLD_AGC_CFG 0XD9
#define REG_HOLD_AGC_BYPASS_VAL_BIT (1<<1)
#define REG_HOLD_AGC_ENABLE_BIT (1<<0)

#define REG_AGC_MANUAL_CFG 0XDA
#define REG_AGC_MANUAL_EN_BIT (1<<7)
#define REG_AGC_MANUAL_SHT_SHIFT 5
#define REG_AGC_MANUAL_SHT_MASK ((1<<2)-1)
#define REG_AGC_MANUAL_STEP_SHIFT 0
#define REG_AGC_MANUAL_STEP_MASK ((1<<5)-1)

#define REG_RFO_DELAY_CFG 0XDB
#define REG_NCO_RFO1_BYPASS_BIT (1<<6)
#define REG_RFO1_DELAY_LEN_SHIFT 4
#define REG_RFO1_DELAY_LEN_MASK ((1<<2)-1)
#define REG_RFO1_CORR_LEN_SHIFT 2
#define REG_RFO1_CORR_LEN_MASK ((1<<2)-1)
#define REG_RFO2_CORR_LEN_SHIFT 0
#define REG_RFO2_CORR_LEN_MASK ((1<<2)-1)

#define REG_FTS_MAX_DELAY_SPREAD_L 0XDC

#define REG_FTS_MAX_DELAY_SPREAD_H 0XDD

#define REG_FTS_EARLY_PATH_L 0XDE

#define REG_FTS_EARLY_PATH_H 0XDF

#define REG_FTS_SECONDARY_PATH_L 0XE0

#define REG_FTS_SECONDARY_PATH_H 0XE1

#define REG_FTS_MAX_PATH_L 0XE2

#define REG_FTS_MAX_PATH_H 0XE3

#define REG_FTS_PRE_NUM 0XE4

#define REG_FTS_TH_SHIFT_CFG 0XE5
#define REG_FTS_INF_SHT_CFG_SHIFT 4
#define REG_FTS_INF_SHT_CFG_MASK ((1<<3)-1)
#define REG_FTS_TH1_IR_SHT_CFG_SHIFT 2
#define REG_FTS_TH1_IR_SHT_CFG_MASK ((1<<2)-1)
#define REG_FTS_TH2_IR_SHT_CFG_SHIFT 0
#define REG_FTS_TH2_IR_SHT_CFG_MASK ((1<<2)-1)

#define REG_TRACK_MODE_THD 0XE6
#define REG_FTS_3RD_THD_SHIFT 4
#define REG_FTS_3RD_THD_MASK ((1<<3)-1)
#define REG_FTS_4TH_THD_BIT (1<<3)
#define REG_FTS_TRACK_SWITCH_THD_SHIFT 0
#define REG_FTS_TRACK_SWITCH_THD_MASK ((1<<3)-1)

#define REG_FTS_COEF_CFG 0XE7
#define REG_FTS_SFO_UNLOCK_THD_SHIFT 3
#define REG_FTS_SFO_UNLOCK_THD_MASK ((1<<3)-1)
#define REG_FTS_ALF_COEF_SHIFT 0
#define REG_FTS_ALF_COEF_MASK ((1<<3)-1)

#define REG_CTRL 0XE8
#define REG_NCO_FREQ_OFT_BYPASS_BIT (1<<7)
#define REG_TS_FULL_MODE_BIT (1<<6)
#define REG_NCO_FREQ_INV_BIT (1<<5)
#define REG_NCO_IFO_BYPASS_BIT (1<<4)
#define REG_FTS_LPC_EN_BIT (1<<3)
#define REG_SFO_FDB_ENABLE_BIT (1<<2)
#define REG_DIF_RS_BYPASS_BIT (1<<1)
#define REG_SFO_ENABLE_BIT (1<<0)

#define REG_OCU_SLICE_MODE_CFG 0XE9
#define REG_SLICE_MODE_BIT (1<<6)
#define REG_SLICE_OFDM_NUM_SHIFT 0
#define REG_SLICE_OFDM_NUM_MASK ((1<<6)-1)

#define REG_SC_VALID_CFG 0XEA
#define REG_TXID_MODE_ENABLE_BIT (1<<6)
#define REG_SC_VALID_SHIFT 0
#define REG_SC_VALID_MASK ((1<<6)-1)

#define REG_SC0_BGN_SLOT 0XEB

#define REG_SC0_NUM 0XEC

#define REG_SC1_BGN_SLOT 0XED

#define REG_SC1_NUM 0XEE

#define REG_SC2_BGN_SLOT 0XEF

#define REG_SC2_NUM 0XF0

#define REG_SC3_BGN_SLOT 0XF1

#define REG_SC3_NUM 0XF2

#define REG_SC4_BGN_SLOT 0XF3

#define REG_SC4_NUM 0XF4

#define REG_SC5_BGN_SLOT 0XF5

#define REG_SC5_NUM 0XF6

#define REG_TIM_VAL 0XF7

#define REG_TIM_TIMEOUT 0XF8

#define REG_DIF_INIT_SFO_H 0XF9

#define REG_DIF_INIT_SFO_M 0XFA

#define REG_DIF_INIT_SFO_L 0XFB

#define REG_SFO_THR 0XFC
#define REG_SFO_TH2_VAL_SHIFT 6
#define REG_SFO_TH2_VAL_MASK ((1<<2)-1)
#define REG_SFO_TH1_VAL_SHIFT 0
#define REG_SFO_TH1_VAL_MASK ((1<<6)-1)

#define REG_SFO_TRACK_CFG 0XFD
#define REG_SFO_TRACK_MODE_SHIFT 6
#define REG_SFO_TRACK_MODE_MASK ((1<<2)-1)
#define REG_SFO_TRACK_TS_NUM_SHIFT 0
#define REG_SFO_TRACK_TS_NUM_MASK ((1<<6)-1)

#define REG_STC_SHT_CFG 0XFE

#define REG_STC_PARA 0XFF
#define REG_STC1_FBIAS_TRACK_EN_BIT (1<<7)
#define REG_STC0_FBIAS_TRACK_EN_BIT (1<<6)
#define REG_STC_NUM_SHIFT 3
#define REG_STC_NUM_MASK ((1<<3)-1)
#define REG_STC_AFLT_COEF_SHIFT 0
#define REG_STC_AFLT_COEF_MASK ((1<<3)-1)

#define REG_CH0_DATA_ADDR 0x80
#define REG_CH1_DATA_ADDR 0x81
#define REG_CH2_DATA_ADDR 0x82
#define REG_CH3_DATA_ADDR 0x83
#define REG_CH4_DATA_ADDR 0x84
#define REG_CH5_DATA_ADDR 0x85
#define REG_COEFF_ADDR 0x99
#define REG_HN_ADDR 0x98

#define TUNER_SLAVE_ADDR 0xd4

#define OCR 0xFFFF00
#define SPI_MAC_RESET_REG 0x06
#define LENGTH_CMD53_NCR_R5_NAC (6+8+2+8)
#define INT_USE_SPI_MAC 0
#define SPI_INT_TYPE 0
#define SPI_BLOCK_LEN 512
#define REG_PAGE_FUNC0 0x00
#define REG_PAGE_FUNC1 0x01
#define CTRL_PATH_READREG 0
#define CTRL_PATH_WRITEREG 1
#define SPI_FIXED_ADDRESS  0
#define SPI_INC_ADDRESS 1

#define SPI_READ_FLAG 0
#define SPI_WRITE_FLAG 1

#define MULTIBYTE_MODE 0
#define BLOCK_MODE 1

#define COEFF_ARRAY_LEN 144

#define DRACO_LVCO 0
#define DRACO_HVCO 1
#define DRACO_CTRL_REG_VAL 0x6a  
#define DRACO_I2CBRATE_CFIG_VAL 0xf
#define DRACO_SALVE_ADDR_VAL 0xd4

#define POLLUX_CTRL_REG_VAL 0x6a  //add by liuyang
#define POLLUX_I2CBRATE_CFIG_VAL 0xf
#define POLLUX_SALVE_ADDR_VAL 0xd4

#define MODE_CONTROL_RTG 0x02
#define SYS_WORK_START_VLD_REG 0x03
#define LPF_MCR_REG 0x11
#define LPF_ICRH_REG 0x13
#define LPF_ICRL_REG 0x14
#define SYN_REC_CPTRL_REG 0x21
#define SYN_PATH_INIT_REG 0x22
#define SYN_PATH_INIT_LOCTRL 0x24
#define SYN_DVD_NUM_REG 0x30
#define SYN_DITHER_REG 0x31
#define SYN_SDM_N3_REG 0x32
#define SYN_SDM_N2_REG 0x33
#define SYN_SDM_N1_REG 0x34
#define SYN_SDM_N0_REG 0x35
#define AFC_CNT_HI_REG 0x67
#define CHIP_STATUS_REG 0x6d

#define NAL_FRAG_THRESH  1430
#define RTP_HDR_LEN 12
#define RTP_PT_H264  96

#define RF_GAIN_ENABLE 0x1d
#define RF_GAIN_DISABLE 0xd
#define RF_GAIN_NUM 0x50
#define BB_DOWN_BOUNDARY 0x6
#define BB_UP_BOUNDARY 0x16
#define BB_DOWN_BOUNDARY_SPUR 0x5
#define BB_UP_BOUNDARY_SPUR 0x16

MXD_RETURN_CODE MXD_API DCC_InitTuner ( MXD_HANDLE hDevice );
 
MXD_RETURN_CODE MXD_API DCC_SetTunerFreq ( MXD_HANDLE hDevice, MXD_UINT32 freqHz );
	
MXD_RETURN_CODE MXD_API DCC_GetTunerStatus ( MXD_HANDLE hDevice );

MXD_RETURN_CODE MXD_API DCC_ReadAfcTable ( MXD_HANDLE hDevice , MXD_UINT32* outFkUhf0, MXD_UINT32* outFkVhf0 );

MXD_RETURN_CODE MXD_API DCC_InitPga ( MXD_HANDLE hDevice );

MXD_UINT8 UTIL_DivToUint24( MXD_UINT32 inDividend,
                 MXD_UINT32 inDivisor,
                 MXD_UINT32 * outQuotientN,
                 MXD_UINT32 * outQuatientFrac
                );
                
MXD_RETURN_CODE MXD_API DCC_FlushReg( MXD_HANDLE hDevice );
/*********Porting functions*****************************************/

/*!
 * \par Description
 * Set config for this demod chip.
 * Notice: This function must be re-implemented to fit different hardware design.
 *
 * \param nDemodChipIndex	[IN] the chip index which host is operating, the first index is 0; if there is only one chip in your system, just ignore it.
 *
 * \return   
 *    MXD_DEVICE_CONFIG	- some config of hardware design, include mpeg2ts interface and I2C interface.
 *
 * \warning    
 */
MXD_DEVICE_CONFIG *MxdPorting_GetDeviceConfig( MXD_UINT8 nDemodChipIndex );

/*!
 * \par Description
 * Write one data to a I2C register of demod chip in host environment.
 * Notice: MIRA is as slave in I2C communication and MIRA slave address is ?; This function must be re-implemented to fit different hardware design.
 *
 * \param nDemodChipIndex	[IN] the chip index which host is operating, the first index is 0;
 * \param addr	[IN] the Register address;
 * \param data	[IN] the register data;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */
MXD_RETURN_CODE MxdPorting_I2C_Write( MXD_UINT8 nDemodChipIndex, MXD_UINT8 slaveAddr, MXD_UINT8 addr, MXD_UINT8* data );

/*!
 * \par Description
 * Read one byte data from a I2C register of demod chip in host environment.
 * Notice: MIRA is as slave in I2C communication and MIRA slave address is ?; This function must be re-implemented to fit different hardware design.
 *
 * \param nDemodChipIndex	[IN] the chip index which host is operating, the first index is 0; if there is only one chip in your system, just ignore it.
 * \param addr	[IN] the Register address;
 * \param data	[OUT] the register data;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */
MXD_RETURN_CODE MxdPorting_I2C_Read( MXD_UINT8 nDemodChipIndex, MXD_UINT8 slaveAddr, MXD_UINT8 addr, MXD_UINT8 *data );

/*!
 * \par Description
 * Transmit and receive some SPI data in host environment.
 * Notice: This function must be re-implemented to fit different hardware design.
 *
 * \param nDemodChipIndex	[IN] the chip index which host is operating, the first index is 0; if there is only one chip in your system, just ignore it.
 * \param trxLen	[IN] the length of data will be transmited and received;
 * \param pDataTx	[IN] the transmiting data;
 * \param pDataRx	[IN] the received data;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */
MXD_RETURN_CODE MxdPorting_SPI_TxRx( MXD_UINT8 nDemodChipIndex, MXD_UINT32 trxLen, MXD_UINT8* pDataTx, MXD_UINT32 revLen, MXD_UINT8* pDataRx );


/*!
 * \par Description
 * Init tuner.
 * Notice: This function must be re-implemented to fit different hardware design.
 *
 * \param nDemodChipIndex	[IN] the chip index which host is operating, the first index is 0; if there is only one chip in your system, just ignore it.
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */
MXD_RETURN_CODE MxdPorting_InitTuner( MXD_HANDLE hDevice );

/*!
 * \par Description
 * Set tuner to frequency.
 * Notice: This function must be re-implemented to fit different hardware design.
 *
 * \param nDemodChipIndex	[IN] the chip index which host is operating, the first index is 0; if there is only one chip in your system, just ignore it.
 * \param freq_khz	[ IN ]	the Tuner freq, unit is khz.
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */
MXD_RETURN_CODE MxdPorting_SetFreq( MXD_HANDLE hDevice, MXD_UINT32 freq_khz );

/*!
 * \par Description
 * Polling tuner status after set tuner to frequency.
 * Notice: This function must be re-implemented to fit different hardware design.
 *
 * \param nDemodChipIndex	[IN] the chip index which host is operating, the first index is 0; if there is only one chip in your system, just ignore it.
 *
 * \return   
 *    MXD_RTN_OK	-	the tuner is 
 *
 * \warning    
 */
MXD_RETURN_CODE MxdPorting_GetTunerStatus( MXD_HANDLE hDevice );

//added by lcj 
MXD_RETURN_CODE MXD_ReadRegFields ( 
    MXD_HANDLE hDevice, 
    MXD_UINT32 regAddr, 
    MXD_UINT8 bitOffset, 
    MXD_UINT8 bitCnt, 
    MXD_UINT8 *pRegVal );

MXD_UINT8 UTIL_BitSet( 
	MXD_UINT8 inputVal, 
    MXD_UINT8 bitOffset, 
    MXD_UINT8 bitCnt, 
    MXD_UINT8 setVal);

MXD_RETURN_CODE MXD_WriteRegFields (
    MXD_HANDLE hDevice, 
    MXD_UINT32 regAddr, 
    MXD_UINT8 bitOffset, 
    MXD_UINT8 bitCnt, 
    MXD_UINT8 regVal );

MXD_RETURN_CODE DTP_ClchProcess(MXD_HANDLE hDevice, MXD_CMMBSERVICE_INFO **ppinfo, MXD_UINT32* pservice_count);
MXD_RETURN_CODE DTP_CaculateBockNum(MXD_HANDLE hDevice, MXD_UINT32 serviceID);

MXD_RETURN_CODE DTP_SetLDPCRSWindow(MXD_HANDLE hDevice);
MXD_RETURN_CODE DTP_GetBler(MXD_HANDLE hDevice,MXD_UINT16* m_bler, MXD_UINT16* m_windowSize);
MXD_RETURN_CODE DTP_GetRSErr(MXD_HANDLE hDevice, MXD_UINT16* m_rsError);
MXD_RETURN_CODE DTP_ServiceDataProcess(MXD_HANDLE hDevice, MXD_UINT8 uIndex, MXD_BOOL bGetServiceName);
MXD_RETURN_CODE DTP_ConfigService(MXD_HANDLE hDevice,  MXD_UINT32 serviceID, MXD_UINT8 Index);
MXD_RETURN_CODE DTP_TrigeServiceReceive(MXD_HANDLE hDevice, MXD_UINT32 serviceID, MXD_UINT8 Index);
MXD_RETURN_CODE DTP_CheckServiceData(MXD_HANDLE hDevice, MXD_UINT8* uIntStatus);
MXD_RETURN_CODE DTP_CheckAvailableDataCount(MXD_HANDLE hDevice, MXD_UINT8 Index, MXD_UINT32*  m_AvailabledataLength);

MXD_RETURN_CODE DTP_StartServiceNameReceive( MXD_HANDLE hDevice );
MXD_RETURN_CODE DTP_StopServiceNameReceive( MXD_HANDLE hDevice );

//end added

MXD_RETURN_CODE MXD_EXPORT MXD_BurstWriteReg( MXD_HANDLE hDevice, MXD_UINT8 regAddr, MXD_UINT8* data, MXD_UINT32 dataLen );
MXD_RETURN_CODE MXD_EXPORT MXD_BurstRead (
    MXD_HANDLE hDevice,
    MXD_UINT8 burstMode,
    MXD_UINT8 bufferAddr,
    MXD_UINT32 burstLen,
    MXD_UINT8 *pBurstDataIn);/*added by liuy*/
/*********End of Porting functions*****************************************/

/*********Top API defines************************************************/
#if 0
typedef enum{
	MIRASTATE_NULL = 0,
	MIRASTATE_IDLE = 100,
	MIRASTATE_BEGINSEARCH,
	MIRASTATE_WAITLOCK,
	MIRASTATE_CHECKSTC,
	MIRASTATE_GETCLCH,
	MIRASTATE_STARTESG,
	MIRASTATE_ESGRECEIVING,
	MIRASTATE_SEARCHDONE,
	MIRASTATE_DATARECEIVING,
	MIRASTATE_STARTRECOVERY,
	MIRASTATE_WAITRECOVERY,
	MIRASTATE_RECOVERYDONE,
}MIRA_SDK_STATE;
#endif
#if 1
    typedef enum{
        MIRASTATE_NULL = 0,
        MIRASTATE_IDLE = 1,
        MIRASTATE_BEGINSEARCH,
        MIRASTATE_WAITLOCK,
        MIRASTATE_CHECKSTC,
        MIRASTATE_GETCLCH,
        MIRASTATE_STARTESG,
        MIRASTATE_ESGRECEIVING,
        MIRASTATE_SEARCHDONE,
        MIRASTATE_DATARECEIVING,
        MIRASTATE_STARTRECOVERY,
        MIRASTATE_WAITRECOVERY,
        MIRASTATE_RECOVERYDONE,
    } MIRA_SDK_STATE;
#endif
typedef struct{
	MXD_UINT8 nDemodChipIndex;
	MXD_DEVICE_CONFIG tDeviceConfig;
	MXD_CALLBACKs m_fnCallbacks;
    MXD_UINT8 *pDevTxBuffer;  /*!<SPI/SDIO TX Temp buffer*/
    MXD_UINT8 *pDevRxBuffer;  /*!<SPI/SDIO RX Temp buffer*/    
	MIRA_SDK_STATE eCurrentState;
	MIRA_SDK_STATE eRequestState;
	void* pRequestStateParam;
	MXD_BOOL bStartServiceSearch;
	struct{
		void* pSearchUserParam;
		MXD_UINT32 nBeginFreqKhz;
		MXD_UINT32 nEndFreqKhz;
		MXD_UINT32 nStepFreqKhz;
		MXD_UINT32 nCurrentFreqKhz;
		MXD_BOOL bGetServiceName;
		MXD_RETURN_CODE eSearchStatus;
		MXD_BOOL bStcStatus;
        MXD_UINT16 nStcRealIdx[2];
		MXD_UINT8 nStcNum;
		MXD_UINT32 nRefTick;
		MXD_UINT32 nAcsTick;
		MXD_UINT32 nSnrTick;
	}ServiceSearchParam;
	MXD_BOOL bSystemLockStatus;
	MXD_BOOL bStartServicePlay;
	MXD_BOOL bStartRecovery;
	MXD_BOOL bRecoveryStatus;
    MXD_BOOL bBigDelayStatus;
    MXD_BOOL bAcsStatus;
    MXD_BOOL bHostMode;
	MXD_BOOL bCLCHEnable;
	MXD_BOOL bSpurExist;
	MXD_UINT8 nBBupBoundary;
	MXD_UINT8 nBBdownBoundary;
    MXD_UINT32 nReSyncNum;
    MXD_INT32 foVal;
	MXD_UINT32 addFo;
	MXD_UINT8 nLastLNA;
    
	struct{
		MXD_UINT32 nActiveServiceID;
		MXD_UINT8 *pRawFrameBuffer;
		MXD_UINT32 nFrameBufLen;
		MXD_UINT8 *pFrameBufferTail;
	//	MXD_UINT32 nReadIndex;
		MXD_UINT32 nBufferLen;
		MXD_BOOL bCorrectDataGot;
	}ActiveService[6];
	MXD_UINT32 nLastStopTick;

	MXD_UINT8 nTickSaved;
	MXD_UINT32 nTickBase;
	MXD_PM_MODE ePowerManagementMode;
	MXD_EMERGENCY_MSG* pLastEmergencyMsg;
	MXD_EMERGENCY_TRIGGER *pLastEmergencyTrigger;
	MXD_VIDEO_PARAM *pLastVideoParam;
	MXD_STREAM_VIDEO_FRAME* pLastVideoFrames;
	MXD_AUDIO_PARAM *pLastAudioParam;
	MXD_STREAM_AUDIO_FRAME* pLastAudioFrames;
	MXD_ESG_DATA *pLastEsgdata;

	void* pDemuxerPrivateStruct;
}MIRA_DEVICE_HANDLE;


typedef void (*MIRA_STATE_FUNC)( MXD_HANDLE hDevice, MIRA_SDK_STATE ePrevState, void* pParam );

typedef struct{
	MIRA_SDK_STATE eState;
	MIRA_STATE_FUNC funcState;
}MIRA_STATE_STRUCT;

void STE_StateProcess( MXD_HANDLE hDevice );
void STE_RequestChangeState( MXD_HANDLE hDevice, MIRA_SDK_STATE eState, void* pParam );

typedef enum{
	FREQ_SEARCH_OK,
	FREQ_SEARCH_FAIL,
}MIRA_SEARCH_RESULT;
/*********End of Top API defines*****************************************/

/*********Demod Chip Controller Layer defines************************************************/

/*!
 * \par Description
 * This function is used to reset device.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */

MXD_RETURN_CODE DCC_ResetDevice( MXD_HANDLE hDevice );

/*!
 * \par Description
 * This function is used to init device.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */

MXD_RETURN_CODE DCC_InitDevice( MXD_HANDLE hDevice );

/*!
 * \par Description
 * This function is used to make chip to sync the signal.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */

MXD_RETURN_CODE DCC_SyncSignal( MXD_HANDLE hDevice );

/*!
 * \par Description
 * This function is used to check sync status.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */

MXD_RETURN_CODE DCC_IsSignalLocked( MXD_HANDLE hDevice );

/*!
 * \par Description
 * This function is used to set sfo and lpc mode when tracking.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */
MXD_RETURN_CODE DCC_SetTrackMode( MXD_HANDLE hDevice );

/*!
 * \par Description
 * This function is used to get signal power.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_UINT8	-	output scale [0-100]
 *
 * \warning    
 */

MXD_INT8 DCC_GetSignalPwr( MXD_HANDLE hDevice );

/*!
 * \par Description
 * This function is used to get system RSSI.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_INT8	-	output scale [-100-0]
 *
 * \warning    
 */

MXD_INT8 DCC_GetSystemRssi( MXD_HANDLE hDevice );

/*!
 * \par Description
 * This function is used to get system SNR.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_UINT8	-	output scale [0-100]
 *
 * \warning    
 */

MXD_UINT8 DCC_GetSystemSnr( MXD_HANDLE hDevice, MXD_SYS_STATUS *sys_status );

/*!
 * \par Description
 * This function is used to get system lock status.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */

MXD_RETURN_CODE DCC_GetSystemStatus( MXD_HANDLE hDevice );

/*!
 * \par Description
 * This function is used to detect single tone.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */

MXD_RETURN_CODE DCC_DetectStc( MXD_HANDLE hDevice );

/*!
 * \par Description
 * This function is used to judge single tone.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */

MXD_RETURN_CODE DCC_IsStcExist( MXD_HANDLE hDevice );

/*!
 * \par Description
 * This function is used to remove single tone.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */

MXD_RETURN_CODE DCC_RemoveStc( MXD_HANDLE hDevice );

/*!
 * \par Description
 * This function is used to config viner coeff manually.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning    
 */
MXD_RETURN_CODE DCC_WriteCoeff( MXD_HANDLE hDevice );

/*!
 * \par Description
 * This function is used to tune freq. this function will return after pll is locked.
 *
 * \param hDevice	[IN] the handle of chip device which host is operating;
 * \param nFreqKhz	[IN] the freqency to tune, unit is khz
 *
 * \return   
 *    MXD_RTN_OK	-	the call succeeded
 *
 * \warning      
 */
MXD_RETURN_CODE MXD_EXPORT DCC_TuneFrequency( MXD_HANDLE hDevice, MXD_UINT32 nFreqKhz );

MXD_UINT32 DCC_GetTickCount( MXD_HANDLE hDevice );
MXD_RETURN_CODE DCC_Sleep( MXD_HANDLE hDevice, MXD_INT32 milliSeconds );
MXD_RETURN_CODE DCC_DetectCheMode( MXD_HANDLE hDevice );
MXD_RETURN_CODE DCC_SearchFrequency( MXD_HANDLE hDevice );
MXD_RETURN_CODE DCC_DetectFo( MXD_HANDLE hDevice );
MXD_RETURN_CODE DCC_UpdatePga( MXD_HANDLE hDevice );
/*********End of Demod Chip Controller Layer defines************************************************/

/*
* added by liuy
*/
/*!
 * \par Description
 * Setup maxscend slave SPI interface, and enable MAC layer of maxscend slave SPI interface.
 *
 * \param hDevice    [ in ] Handle of the device
 *
 * \return Return code by MXD_RETURN_CODE enumeration
 *
 *
 * \remarks:
 *
 */
MXD_RETURN_CODE MXD_API DDS_SetupMxdSpi ( MXD_HANDLE hDevice );

/*!
 * Stop and set it into idle state.
 *
 * \param hDevice    [ in ] Handle of the device
 *
 * \return Return code by MXD_RETURN_CODE enumeration
 *
 *
 * \remarks:
 *
 */
MXD_RETURN_CODE MXD_API DDS_StopMxdSpi ( MXD_HANDLE hDevice );

/*!
 * \par Description
 * Cmd52 in MAC layer of maxscend SPI interface, and it is for byte read/write.
 *
 * \param hDevice       [ in ] Handle of the device
 * \param rwIndicator   [ in ] Read/Write Indicator. ( SPI_BYTE_READ and SPI_BYTE_WRITE )
 * \param regFuncNum    [ in ] Register function/page no. to be read.
 * \param regAddr               [ in ] Register address to be read.
 * \param pRegVal               [ inout ] Pointer to the register value, which will be written or should be read.
 *
 * \return Return code by MXD_RETURN_CODE enumeration
 *
 *
 * \remarks:
 *   Response5 format is:
 *             ЩЩЩЩЩЩЩЩ
 *              0  0       0   R/W data(8bits)     
 *             ةةةةةةةة
 *              For more detail to see Page22 of SimplifiedSDIOCardSpecification1.10
 *
 */
 
MXD_RETURN_CODE MXD_API DDS_SpiCmd52( MXD_HANDLE hDevice, MXD_UINT8 rwIndicator, MXD_UINT8 regFuncNum, MXD_UINT32 regAddr, MXD_UINT8 *pRegVal );

/*!
 * \par Description
 * Cmd53 in MAC layer of maxscend SPI interface, and it is for burst read only.
 *
 * \param hDevice               [ in ] Handle of the device
 * \param rwFlag				[ in ] read / write flag: ( SPI_READ_FLAG and SPI_WRITE_FLAG )
 * \param burstMode             [ in ] Burst read mode: ( SPI_BLOCK_READ and SPI_MULTIBYTE_READ )
 * \param bufferAddr            [ in ] On-chip buffer address to be read.
 * \param byteCnt                       [ in ] Bytes to be read, it should be even.
 * \param pBurstDataIn          [ out ] Pointer to the burst data after reading.
 *
 * \return Return code by MXD_RETURN_CODE enumeration
 *
 *
 * \remarks:
 *
 */
MXD_RETURN_CODE MXD_API DDS_SpiCmd53 ( MXD_HANDLE hDevice, MXD_UINT8 rwFlag, MXD_UINT8 burstMode, MXD_UINT32 bufferAddr, MXD_UINT16 byteCnt, MXD_UINT8 *pBurstDataIn );

/*!
 * \par Description
 * Tx/Rx of master SPI, it will be porting according to different host processor.
 *
 * \param hDevice               [ in ] Handle of the device
 * \param trxLen                        [ in ] length to be txed or rxed
 * \param pDataOut              [ in ] pointer to the data to be txed.
 * \param pDataIn                       [ out ] pointer to the data to be rxed.
 *
 * \return Return code by MHL_DRV_RTN_CODE_E enumeration
 *
 *
 * \remarks: it will be porting according to different host processor.
 *
 */
MXD_RETURN_CODE MXD_API DDS_MasterSpiTxRx( MXD_HANDLE hDevice, MXD_UINT32 trxLen, MXD_UINT8 *pDataOut, MXD_UINT32 revLen, MXD_UINT8 *pDataIn );

    
#ifdef __cplusplus
}
#endif

#endif /* __MIRA_PRIVATE_H__ */

/* end of Mxd0250Private.h */
